Let's be clear about one thing first: the Chinese government's stated goal of training frontier AI models exclusively on domestic hardware by 2028 is not a political statement. It is a systems engineering problem with a hard deadline. And the data suggests that while the single-card performance gap is closing faster than most Western analysts admit, the real bottleneck lies in the plumbing—the interconnect fabric, the software stack, and the cold, hard physics of power delivery.
This is not about geopolitics. It is about latency, throughput, and the unglamorous reality of cluster utilization rates (MFU). If you strip away the rhetoric, this is a massive, state-backed refactor of a national compute stack, and the legacy dependencies are brutal.
Context: The Hardware Has Caught Up; The System Has Not
For years, the narrative was simple: Chinese chips were five years behind NVIDIA. That narrative is now outdated. Based on my audits and the public benchmark data from late 2024, Huawei's Ascend 910B delivers roughly 320 TFLOPS in FP16, which is statistically indistinguishable from the A100's 312 TFLOPS. The upcoming 910C is expected to hit 70-80% of an H100's raw throughput. Cambricon's Siyuan 590 has achieved near-parity in energy efficiency for training workloads.
These are not trivial gains. They represent a decade of aggressive architectural iteration, largely through Chiplet stacking and optimized memory hierarchies to compensate for the lack of advanced process nodes. In a single-GPU benchmark, the "China gap" is nearly closed.
However, as any protocol developer will tell you, a node is not a network. The gap in single-card performance is irrelevant if you cannot scale to 10,000 cards without losing 30% of your theoretical throughput to communication overhead.
Core: The Cluster Interconnect is the Achilles' Heel
Let's dissect the actual bottleneck. NVIDIA's dominance is not the GPU; it is the NVLink/NVSwitch fabric combined with InfiniBand RDMA networking. This provides up to 900GB/s of interconnect bandwidth between dies. Huawei's HCCS with RoCEv2 networking tops out at roughly 400-500GB/s. This is a 50% reduction in inter-node bandwidth, and in large-scale synchronous training (Megatron-DeepSpeed style), bandwidth directly translates to training wall-clock time.
My own experience with distributed systems during the DeFi Summer audits taught me that state synchronization is where bugs and inefficiencies hide. In AI training, the "state" is the gradient. If the gradient synchronization pipeline is starved for bandwidth, the entire cluster idles. Industry estimates suggest that domestic Chinese clusters currently achieve a linear scaling efficiency of 70-85% at the 1,000-card level. The 2028 target demands 90%+ efficiency at the 10,000-card level. That is not an incremental improvement; that is a fundamental refactor of the network stack.
Then there is the MFU problem. This is the metric that matters but is rarely discussed outside engineering circles. Model FLOPs Utilization measures how much of your theoretical peak compute is actually used. NVIDIA clusters routinely hit 50-60% MFU on frontier models. Chinese domestic clusters, by most estimates, sit at 30-40%. This is the hidden tax of software immaturity. It means a 10,000-card domestic cluster delivers the same effective compute as a 6,000-card NVIDIA cluster. To hit the 2028 target, China needs to not only build the hardware but also optimize the CUDA-equivalent software stack—the CANN platform and MindSpore framework—to squeeze out another 20 points of MFU. Code does not lie, but it often forgets to breathe.
Contrarian: The Security Blind Spot is the Memory Wall, Not the Process Node
Most geopolitical analysis focuses on the US export controls on advanced lithography. That is the wrong place to look. The immediate, existential threat to the 2028 roadmap is not the EUV lithography machine; it is HBM (High Bandwidth Memory).
The Ascend 910B relies on HBM2E/HBM3 supplied by Samsung and SK Hynix. If the US expands export controls to cover HBM (as has been hinted), the Chinese AI chip industry faces a sudden memory wall. The performance gains of the last two years were achieved not just through clever architecture but through massive amounts of memory bandwidth. Without HBM, the Chiplet strategy collapses. Domestic HBM production (via CXMT) is still in the lab phase. The entire 2028 timeline hinges on whether China can industrialize HBM production in under 36 months. This is a supply chain risk that is rarely highlighted but is far more critical than the process node issue.
Furthermore, the definition of "frontier" is conveniently elastic. If the target is to train a GPT-4 level model from 2024, the 2028 goal is conservative and achievable. If the target is to match the SOTA of 2028, the compute requirement jumps by two orders of magnitude (10^26 to 10^27 FLOPs). The plan likely aims for the former while implying the latter—a classic ambiguity that gives policymakers room to maneuver.
Takeaway: The Real Output is a Dual Compute Ecosystem
The 2028 deadline is not the finish line; it is the mid-point check. The realistic outcome is not the destruction of NVIDIA's ecosystem but the formalization of a parallel, self-contained compute ecosystem. The global AI market will bifurcate into two standards: the NVIDIA/CUDA stack and the Huawei/CANN stack. For developers, this means double the integration work. For infrastructure investors, it means the "China compute" narrative is a distinct asset class with different risk parameters.
We are entering an era of compute sovereignty. The question is not whether China will build a 10,000-card cluster; it is whether the MFU of that cluster will be high enough to justify the capital expenditure. Based on the current trajectory, the hardware will be ready. The software will not. And that is the only variable that matters.
Gas wars are just ego masquerading as utility; in this case, the gas is the gradient sync, and the ego is national pride.